Gecko [ aodai.devttt.com ]

Name	Size	Permission
ac97	[ DIR ]	drwxr-xr-x
sof	[ DIR ]	drwxr-xr-x
ac97_codec.h	15.67 KB	-rw-r--r--
aci.h	2.4 KB	-rw-r--r--
ad1816a.h	4.73 KB	-rw-r--r--
ad1843.h	1.48 KB	-rw-r--r--
adau1373.h	706 B	-rw-r--r--
ak4113.h	10.22 KB	-rw-r--r--
ak4114.h	9.54 KB	-rw-r--r--
ak4117.h	8.34 KB	-rw-r--r--
ak4531_codec.h	2.42 KB	-rw-r--r--
ak4641.h	476 B	-rw-r--r--
ak4xxx-adda.h	2.66 KB	-rw-r--r--
alc5623.h	536 B	-rw-r--r--
asequencer.h	2.91 KB	-rw-r--r--
asound.h	590 B	-rw-r--r--
asoundef.h	16.02 KB	-rw-r--r--
compress_driver.h	7.8 KB	-rw-r--r--
control.h	9.72 KB	-rw-r--r--
core.h	15.52 KB	-rw-r--r--
cs35l33.h	888 B	-rw-r--r--
cs35l34.h	741 B	-rw-r--r--
cs35l35.h	2.21 KB	-rw-r--r--
cs35l36.h	772 B	-rw-r--r--
cs35l41.h	30.17 KB	-rw-r--r--
cs4231-regs.h	7.6 KB	-rw-r--r--
cs4271.h	961 B	-rw-r--r--
cs42l42.h	34.33 KB	-rw-r--r--
cs42l52.h	592 B	-rw-r--r--
cs42l56.h	1.02 KB	-rw-r--r--
cs42l73.h	361 B	-rw-r--r--
cs8403.h	7.95 KB	-rw-r--r--
cs8427.h	9.72 KB	-rw-r--r--
da7213.h	1.01 KB	-rw-r--r--
da7218.h	2.41 KB	-rw-r--r--
da7219-aad.h	2.21 KB	-rw-r--r--
da7219.h	998 B	-rw-r--r--
da9055.h	707 B	-rw-r--r--
designware_i2s.h	1.59 KB	-rw-r--r--
dmaengine_pcm.h	6.75 KB	-rw-r--r--
emu10k1.h	88.6 KB	-rw-r--r--
emu10k1_synth.h	693 B	-rw-r--r--
emu8000.h	3.25 KB	-rw-r--r--
emu8000_reg.h	9.54 KB	-rw-r--r--
emux_legacy.h	4.7 KB	-rw-r--r--
emux_synth.h	6.79 KB	-rw-r--r--
es1688.h	2.85 KB	-rw-r--r--
graph_card.h	271 B	-rw-r--r--
gus.h	19.65 KB	-rw-r--r--
hda_chmap.h	2.6 KB	-rw-r--r--
hda_codec.h	17.25 KB	-rw-r--r--
hda_component.h	2.04 KB	-rw-r--r--
hda_hwdep.h	736 B	-rw-r--r--
hda_i915.h	589 B	-rw-r--r--
hda_register.h	10.41 KB	-rw-r--r--
hda_regmap.h	6.77 KB	-rw-r--r--
hda_verbs.h	16.89 KB	-rw-r--r--
hdaudio.h	21.03 KB	-rw-r--r--
hdaudio_ext.h	5.55 KB	-rw-r--r--
hdmi-codec.h	2.94 KB	-rw-r--r--
hwdep.h	1.88 KB	-rw-r--r--
i2c.h	2.79 KB	-rw-r--r--
info.h	7.86 KB	-rw-r--r--
initval.h	2.43 KB	-rw-r--r--
intel-dsp-config.h	869 B	-rw-r--r--
intel-nhlt.h	2.78 KB	-rw-r--r--
jack.h	3.1 KB	-rw-r--r--
l3.h	524 B	-rw-r--r--
madera-pdata.h	1.95 KB	-rw-r--r--
max9768.h	729 B	-rw-r--r--
max98088.h	1.05 KB	-rw-r--r--
max98090.h	534 B	-rw-r--r--
max98095.h	1.33 KB	-rw-r--r--
memalloc.h	2.58 KB	-rw-r--r--
minors.h	3.65 KB	-rw-r--r--
mixer_oss.h	1.73 KB	-rw-r--r--
mpu401.h	3.81 KB	-rw-r--r--
omap-hdmi-audio.h	971 B	-rw-r--r--
opl3.h	11.63 KB	-rw-r--r--
opl4.h	459 B	-rw-r--r--
pcm-indirect.h	5.04 KB	-rw-r--r--
pcm.h	52.43 KB	-rw-r--r--
pcm_drm_eld.h	183 B	-rw-r--r--
pcm_iec958.h	597 B	-rw-r--r--
pcm_oss.h	2.01 KB	-rw-r--r--
pcm_params.h	8.66 KB	-rw-r--r--
pt2258.h	513 B	-rw-r--r--
pxa2xx-lib.h	2.14 KB	-rw-r--r--
rawmidi.h	5.74 KB	-rw-r--r--
rt1015.h	283 B	-rw-r--r--
rt286.h	314 B	-rw-r--r--
rt298.h	373 B	-rw-r--r--
rt5514.h	399 B	-rw-r--r--
rt5659.h	880 B	-rw-r--r--
rt5660.h	578 B	-rw-r--r--
rt5663.h	476 B	-rw-r--r--
rt5665.h	761 B	-rw-r--r--
rt5668.h	646 B	-rw-r--r--
rt5682.h	901 B	-rw-r--r--
s3c24xx_uda134x.h	229 B	-rw-r--r--
sb.h	10.3 KB	-rw-r--r--
sb16_csp.h	2.05 KB	-rw-r--r--
seq_device.h	2.11 KB	-rw-r--r--
seq_kernel.h	3.3 KB	-rw-r--r--
seq_midi_emul.h	6.6 KB	-rw-r--r--
seq_midi_event.h	1.32 KB	-rw-r--r--
seq_oss.h	2.21 KB	-rw-r--r--
seq_oss_legacy.h	360 B	-rw-r--r--
seq_virmidi.h	2.07 KB	-rw-r--r--
sh_dac_audio.h	441 B	-rw-r--r--
sh_fsi.h	693 B	-rw-r--r--
simple_card.h	529 B	-rw-r--r--
simple_card_utils.h	8.16 KB	-rw-r--r--
snd_wavefront.h	5.57 KB	-rw-r--r--
soc-acpi-intel-match.h	2.03 KB	-rw-r--r--
soc-acpi.h	5.5 KB	-rw-r--r--
soc-card.h	2.88 KB	-rw-r--r--
soc-component.h	18.93 KB	-rw-r--r--
soc-dai.h	19.07 KB	-rw-r--r--
soc-dapm.h	32.18 KB	-rw-r--r--
soc-dpcm.h	5.39 KB	-rw-r--r--
soc-jack.h	3.73 KB	-rw-r--r--
soc-link.h	1.14 KB	-rw-r--r--
soc-topology.h	5.7 KB	-rw-r--r--
soc.h	46.78 KB	-rw-r--r--
sof.h	2.54 KB	-rw-r--r--
soundfont.h	3.81 KB	-rw-r--r--
spear_dma.h	350 B	-rw-r--r--
spear_spdif.h	345 B	-rw-r--r--
sta32x.h	1015 B	-rw-r--r--
sta350.h	1.44 KB	-rw-r--r--
tas2552-plat.h	283 B	-rw-r--r--
tas5086.h	210 B	-rw-r--r--
tea6330t.h	468 B	-rw-r--r--
timer.h	4.99 KB	-rw-r--r--
tlv.h	1.59 KB	-rw-r--r--
tlv320aic32x4.h	1.29 KB	-rw-r--r--
tlv320aic3x.h	1.74 KB	-rw-r--r--
tlv320dac33-plat.h	574 B	-rw-r--r--
tpa6130a2-plat.h	291 B	-rw-r--r--
uda134x.h	451 B	-rw-r--r--
uda1380.h	335 B	-rw-r--r--
util_mem.h	1.58 KB	-rw-r--r--
vx_core.h	14.7 KB	-rw-r--r--
wavefront.h	18.08 KB	-rw-r--r--
wm0010.h	466 B	-rw-r--r--
wm1250-ev1.h	510 B	-rw-r--r--
wm2000.h	479 B	-rw-r--r--
wm2200.h	1.32 KB	-rw-r--r--
wm5100.h	1.1 KB	-rw-r--r--
wm8903.h	15.02 KB	-rw-r--r--
wm8904.h	7.22 KB	-rw-r--r--
wm8955.h	442 B	-rw-r--r--
wm8960.h	888 B	-rw-r--r--
wm8962.h	1.65 KB	-rw-r--r--
wm8993.h	1.05 KB	-rw-r--r--
wm8996.h	1.26 KB	-rw-r--r--
wm9081.h	515 B	-rw-r--r--
wm9090.h	634 B	-rw-r--r--
wss.h	7.76 KB	-rw-r--r--

Code Editor : hda_register.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * HD-audio controller (Azalia) registers and helpers
 *
 * For traditional reasons, we still use azx_ prefix here
 */

#ifndef __SOUND_HDA_REGISTER_H
#define __SOUND_HDA_REGISTER_H

#include <linux/io.h>
#include <sound/hdaudio.h>

#define AZX_REG_GCAP			0x00
#define   AZX_GCAP_64OK		(1 << 0)   /* 64bit address support */
#define   AZX_GCAP_NSDO		(3 << 1)   /* # of serial data out signals */
#define   AZX_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   AZX_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   AZX_GCAP_OSS		(15 << 12) /* # of output streams */
#define AZX_REG_VMIN			0x02
#define AZX_REG_VMAJ			0x03
#define AZX_REG_OUTPAY			0x04
#define AZX_REG_INPAY			0x06
#define AZX_REG_GCTL			0x08
#define   AZX_GCTL_RESET	(1 << 0)   /* controller reset */
#define   AZX_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   AZX_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
#define AZX_REG_WAKEEN			0x0c
#define AZX_REG_STATESTS		0x0e
#define AZX_REG_GSTS			0x10
#define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */
#define AZX_REG_GCAP2			0x12
#define AZX_REG_LLCH			0x14
#define AZX_REG_OUTSTRMPAY		0x18
#define AZX_REG_INSTRMPAY		0x1A
#define AZX_REG_INTCTL			0x20
#define AZX_REG_INTSTS			0x24
#define AZX_REG_WALLCLK			0x30	/* 24Mhz source */
#define AZX_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define AZX_REG_SSYNC			0x38
#define AZX_REG_CORBLBASE		0x40
#define AZX_REG_CORBUBASE		0x44
#define AZX_REG_CORBWP			0x48
#define AZX_REG_CORBRP			0x4a
#define   AZX_CORBRP_RST	(1 << 15)  /* read pointer reset */
#define AZX_REG_CORBCTL			0x4c
#define   AZX_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   AZX_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
#define AZX_REG_CORBSTS			0x4d
#define   AZX_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
#define AZX_REG_CORBSIZE		0x4e

#define AZX_REG_RIRBLBASE		0x50
#define AZX_REG_RIRBUBASE		0x54
#define AZX_REG_RIRBWP			0x58
#define   AZX_RIRBWP_RST	(1 << 15)  /* write pointer reset */
#define AZX_REG_RINTCNT			0x5a
#define AZX_REG_RIRBCTL			0x5c
#define   AZX_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   AZX_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   AZX_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
#define AZX_REG_RIRBSTS			0x5d
#define   AZX_RBSTS_IRQ		(1 << 0)   /* response irq */
#define   AZX_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
#define AZX_REG_RIRBSIZE		0x5e

#define AZX_REG_IC			0x60
#define AZX_REG_IR			0x64
#define AZX_REG_IRS			0x68
#define   AZX_IRS_VALID		(1<<1)
#define   AZX_IRS_BUSY		(1<<0)

#define AZX_REG_DPLBASE			0x70
#define AZX_REG_DPUBASE			0x74
#define   AZX_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define AZX_REG_SD_CTL			0x00
#define AZX_REG_SD_CTL_3B		0x02 /* 3rd byte of SD_CTL register */
#define AZX_REG_SD_STS			0x03
#define AZX_REG_SD_LPIB			0x04
#define AZX_REG_SD_CBL			0x08
#define AZX_REG_SD_LVI			0x0c
#define AZX_REG_SD_FIFOW		0x0e
#define AZX_REG_SD_FIFOSIZE		0x10
#define AZX_REG_SD_FORMAT		0x12
#define AZX_REG_SD_FIFOL		0x14
#define AZX_REG_SD_BDLPL		0x18
#define AZX_REG_SD_BDLPU		0x1c

/* GTS registers */
#define AZX_REG_LLCH			0x14

#define AZX_REG_GTS_BASE		0x520

#define AZX_REG_GTSCC	(AZX_REG_GTS_BASE + 0x00)
#define AZX_REG_WALFCC	(AZX_REG_GTS_BASE + 0x04)
#define AZX_REG_TSCCL	(AZX_REG_GTS_BASE + 0x08)
#define AZX_REG_TSCCU	(AZX_REG_GTS_BASE + 0x0C)
#define AZX_REG_LLPFOC	(AZX_REG_GTS_BASE + 0x14)
#define AZX_REG_LLPCL	(AZX_REG_GTS_BASE + 0x18)
#define AZX_REG_LLPCU	(AZX_REG_GTS_BASE + 0x1C)

/* Haswell/Broadwell display HD-A controller Extended Mode registers */
#define AZX_REG_HSW_EM4			0x100c
#define AZX_REG_HSW_EM5			0x1010

/* Skylake/Broxton vendor-specific registers */
#define AZX_REG_VS_EM1			0x1000
#define AZX_REG_VS_INRC			0x1004
#define AZX_REG_VS_OUTRC		0x1008
#define AZX_REG_VS_FIFOTRK		0x100C
#define AZX_REG_VS_FIFOTRK2		0x1010
#define AZX_REG_VS_EM2			0x1030
#define AZX_REG_VS_EM3L			0x1038
#define AZX_REG_VS_EM3U			0x103C
#define AZX_REG_VS_EM4L			0x1040
#define AZX_REG_VS_EM4U			0x1044
#define AZX_REG_VS_LTRP			0x1048
#define AZX_REG_VS_D0I3C		0x104A
#define AZX_REG_VS_PCE			0x104B
#define AZX_REG_VS_L2MAGC		0x1050
#define AZX_REG_VS_L2LAHPT		0x1054
#define AZX_REG_VS_SDXDPIB_XBASE	0x1084
#define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20
#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20

/* PCI space */
#define AZX_PCIREG_TCSEL		0x44

/*
 * other constants
 */

/* max number of fragments - we may use more if allocating more pages for BDL */
#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
/*
 * max buffer size - artificial 4MB limit per stream to avoid big allocations
 * In theory it can be really big, but as it is per stream on systems with many streams memory could
 * be quickly saturated if userspace requests maximum buffer size for each of them.
 */
#define AZX_MAX_BUF_SIZE	(4*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define STATESTS_INT_MASK	((1 << HDA_MAX_CODECS) - 1)

/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)
#define SD_CTL_STRIPE_MASK	0x3	/* stripe control mask */

/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
#define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */
#define AZX_MAX_CORB_ENTRIES	256
#define AZX_MAX_RIRB_ENTRIES	256

/* Capability header  Structure */
#define AZX_REG_CAP_HDR			0x0
#define AZX_CAP_HDR_VER_OFF		28
#define AZX_CAP_HDR_VER_MASK		(0xF << AZX_CAP_HDR_VER_OFF)
#define AZX_CAP_HDR_ID_OFF		16
#define AZX_CAP_HDR_ID_MASK		(0xFFF << AZX_CAP_HDR_ID_OFF)
#define AZX_CAP_HDR_NXT_PTR_MASK	0xFFFF

/* registers of Software Position Based FIFO Capability Structure */
#define AZX_SPB_CAP_ID			0x4
#define AZX_REG_SPB_BASE_ADDR		0x700
#define AZX_REG_SPB_SPBFCH		0x00
#define AZX_REG_SPB_SPBFCCTL		0x04
/* Base used to calculate the iterating register offset */
#define AZX_SPB_BASE			0x08
/* Interval used to calculate the iterating register offset */
#define AZX_SPB_INTERVAL		0x08
/* SPIB base */
#define AZX_SPB_SPIB			0x00
/* SPIB MAXFIFO base*/
#define AZX_SPB_MAXFIFO			0x04

/* registers of Global Time Synchronization Capability Structure */
#define AZX_GTS_CAP_ID			0x1
#define AZX_REG_GTS_GTSCH		0x00
#define AZX_REG_GTS_GTSCD		0x04
#define AZX_REG_GTS_GTSCTLAC		0x0C
#define AZX_GTS_BASE			0x20
#define AZX_GTS_INTERVAL		0x20

/* registers for Processing Pipe Capability Structure */
#define AZX_PP_CAP_ID			0x3
#define AZX_REG_PP_PPCH			0x10
#define AZX_REG_PP_PPCTL		0x04
#define AZX_PPCTL_PIE			(1<<31)
#define AZX_PPCTL_GPROCEN		(1<<30)
/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
#define AZX_PPCTL_PROCEN(_X_)		(1<<(_X_))

#define AZX_REG_PP_PPSTS		0x08

#define AZX_PPHC_BASE			0x10
#define AZX_PPHC_INTERVAL		0x10

#define AZX_REG_PPHCLLPL		0x0
#define AZX_REG_PPHCLLPU		0x4
#define AZX_REG_PPHCLDPL		0x8
#define AZX_REG_PPHCLDPU		0xC

#define AZX_PPLC_BASE			0x10
#define AZX_PPLC_MULTI			0x10
#define AZX_PPLC_INTERVAL		0x10

#define AZX_REG_PPLCCTL			0x0
#define AZX_PPLCCTL_STRM_BITS		4
#define AZX_PPLCCTL_STRM_SHIFT		20
#define AZX_REG_MASK(bit_num, offset) \
	(((1 << (bit_num)) - 1) << (offset))
#define AZX_PPLCCTL_STRM_MASK \
	AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
#define AZX_PPLCCTL_RUN			(1<<1)
#define AZX_PPLCCTL_STRST		(1<<0)

#define AZX_REG_PPLCFMT			0x4
#define AZX_REG_PPLCLLPL		0x8
#define AZX_REG_PPLCLLPU		0xC

/* registers for Multiple Links Capability Structure */
#define AZX_ML_CAP_ID			0x2
#define AZX_REG_ML_MLCH			0x00
#define AZX_REG_ML_MLCD			0x04
#define AZX_ML_BASE			0x40
#define AZX_ML_INTERVAL			0x40

#define AZX_REG_ML_LCAP			0x00
#define AZX_REG_ML_LCTL			0x04
#define AZX_REG_ML_LOSIDV		0x08
#define AZX_REG_ML_LSDIID		0x0C
#define AZX_REG_ML_LPSOO		0x10
#define AZX_REG_ML_LPSIO		0x12
#define AZX_REG_ML_LWALFC		0x18
#define AZX_REG_ML_LOUTPAY		0x20
#define AZX_REG_ML_LINPAY		0x30

/* bit0 is reserved, with BIT(1) mapping to stream1 */
#define ML_LOSIDV_STREAM_MASK		0xFFFE

#define ML_LCTL_SCF_MASK			0xF
#define AZX_MLCTL_SPA				(0x1 << 16)
#define AZX_MLCTL_CPA				(0x1 << 23)
#define AZX_MLCTL_SPA_SHIFT			16
#define AZX_MLCTL_CPA_SHIFT			23

/* registers for DMA Resume Capability Structure */
#define AZX_DRSM_CAP_ID			0x5
#define AZX_REG_DRSM_CTL		0x4
/* Base used to calculate the iterating register offset */
#define AZX_DRSM_BASE			0x08
/* Interval used to calculate the iterating register offset */
#define AZX_DRSM_INTERVAL		0x08

/* Global time synchronization registers */
#define GTSCC_TSCCD_MASK		0x80000000
#define GTSCC_TSCCD_SHIFT		BIT(31)
#define GTSCC_TSCCI_MASK		0x20
#define GTSCC_CDMAS_DMA_DIR_SHIFT	4

#define WALFCC_CIF_MASK			0x1FF
#define WALFCC_FN_SHIFT			9
#define HDA_CLK_CYCLES_PER_FRAME	512

/*
 * An error occurs near frame "rollover". The clocks in frame value indicates
 * whether this error may have occurred. Here we use the value of 10. Please
 * see the errata for the right number [<10]
 */
#define HDA_MAX_CYCLE_VALUE		499
#define HDA_MAX_CYCLE_OFFSET		10
#define HDA_MAX_CYCLE_READ_RETRY	10

#define TSCCU_CCU_SHIFT			32
#define LLPC_CCU_SHIFT			32

/*
 * helpers to read the stream position
 */
static inline unsigned int
snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
{
	return snd_hdac_stream_readl(stream, SD_LPIB);
}

static inline unsigned int
snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
{
	return le32_to_cpu(*stream->posbuf);
}

#endif /* __SOUND_HDA_REGISTER_H */

${this.title}

Code Editor : hda_register.h